Limerick(3) - SpinalHDL Tutorial: Setting up the Development Environment
Hello, everyone. Welcome to the third episode of FPGA
limerick. In this episode, we will get hands-on for SpinalHDL, starting by setting
up the Development Environment.
Setup for Windows/MSYS2
As mentioned in the first episode, we will use Windows 11 +
MSYS2 + WSL2 as our host platform. And we will start by MSYS2 first. To install MSYS2, please open your browser
and go to https://www.msys2.org/
And at this point, we will install the following version for MSYS2:
One thing I want to mention is that you will find similar
steps on SpinalHDL’s official website. But it seems those steps on the official
website is not up-to-date. So please follow the steps listed above exactly. This is especially true for the last step above when you try
to install verilator.
Ok. Now after the last step to install verilator, you can
close the MSYS2 window, and the put the following two paths in the system path:
(From the start menu, you can choose settings / system / about
/ advanced system settings, then choose environment variables
Double-click the path in system variables, click new and copy
paste those two paths. Please make sure those two paths are at the top of the
Setup for Windows/SBT
Now, at this point, we are done with the MSYS2.And next we will install the SBT. Please open
your browser and go to https://www.scala-sbt.org/
And currently we are using SBT 1.8.2 for Windows, which can
be directly downloaded from the following path:
Limerick(2) - Why SpinalHDL? The History of HDL/HVL
Hello, everyone. Welcome to the second episode of FPGA limerick. In this episode, we will talk about the benefit of SpinalHDL. And we will start by visiting the evolution history of HDL (Hardware Description Language).
History 101 for HDL/HVL
In the beginning of time when digital circuits started to emerge, everything was handcrafted. A typical example of such design practice is the ubiquitous presence of Texas Instruments’ 74-Series IC back then. At that time, a large digital circuit was usually composed of multiple discrete ICs (AND gate, OR gate, FlipFlop etc.). And the whole system was often bulky and slow.
But as Moore’s law settles in, the scale of digital circuit grew exponentially over the years. It calls for a better methodology and automation in design. And thus comes in the hardware description language.
The first hardware description language is VHDL. It was developed in 1983 under the funding of the Department of Defense. It was such a big deal at that time, and the VHDL was put under export control initially. As of today, a lot of US defense companies still use VHDL due to their DoD legacy.
At the same time, Verilog also emerged in the commercial world. Verilog was introduced by a company called Gateway Design Automation in 1984. (This company was later acquired by Cadence.). It offers similar design features to VHDL, but in a more concise fashion.
Oh! At this point, please allow me to hit a tangent on this. Because people often ask me: Between VHDL and Verilog, which one you think is better? And my answer is the following:
First of all, most of the time, you probably don’t have the privilege to choose. As for those well-established companies, the decision was made long time ago when the design team was initially formed. And libraries and code were created based that choice since then. New designs will always gravitate toward the same language for the sake of code reuse.
However, if you do have the chance to choose between VHDL and Verilog, I would recommend Verilog over VHDL for the following reasons:
a) VHDL is a strong typed language while Verilog is not. To use programming language as analogy, VHDL to Verilog is what Pascal to C. However, since VHDL and Verilog are both intended to describe hardware, every value eventually boils down to ones and zeros. The strong type offers little help besides making things awkward. And modern lint tools can do a much better job without using strong type.
b) The evolution of VHDL is lagging behind that of Verilog. Many useful features of Verilog 2001 can only find their counterparts in VHDL 2008. Wildcard and external names are two of the conspicuous examples.
c) Both VHDL and Verilog are weak on verification. In the early days, they have to rely on other languages, such as Vera, e or even tcl, for more advanced verification. But Verilog made up for this by upgrading itself to Systemverilog. As a superset of Verilog, Systemverilog is rich in features to enhance verification.
d) For gate level simulation, Verilog holds a performance advantage over VHDL, because it has built-in primitives to describe gate level components. While VHDL has to rely on VITAL library in this regard. As a result of that, most 3rd party simulation libraries are in Verilog. So if your design is in VHDL, you have to acquire a mixed language license in addition to your existing VHDL license when you simulate a design that contains 3rd party library. As you might know, EDA licenses are notoriously expensive!
OK, let’s go back to our history lesson. After the VHDL / Verilog appeared in 1980s, the size of the design gets bigger and bigger. And their weakness on verification becomes prominent. So in 1990s, HVL (Hardware Verification Language) were introduced. The first HVL was Vera by Sun Microsystems in 1995. Followed by e language in 1996. And the Vera later turned into OpenVera, which becomes the foundation of SystemVerilog
And in 2001, the HDL and HVL finally merged into one language called SystemVerilog. The SystemVerilog borrowed pages from a lot of other languages, and it supports class for Object Oriented feature. And it also has interface feature for transaction level simulation. The UVM standard is also mainly based on SystemVerilog (Which is the random verification approach by introducing random stimulus and comparing the result with reference model.)
And around the same time, those folks in the CS (Computer Science) world starts to get their hands on the HDL/HVL as well. Now come to think of it, every digital component, such as NAND gate, Flip-Flop can all be modelled as a class. In that sense, the digital design and verification can all be accomplished using high level programming language, such as C++. This approach is also favored by system designers, as the system model is often in C++. With the System C, everything (all the way from system design to RTL design) can be completed using C++ only. That is a brilliant idea by itself!
However, due to the combination of multiple unfavorable circumstances, System C did not pan out. In particular, it failed to win the hearts of FPGA vendors. As of today, the main stream FPGA vendors (both AMD and Intel) only accept VHDL, Verilog and SystemVerilog as input for synthesis.
The reason for System C’s unpopularity is still up to debate. And here is an answer provided by ChatGPT.
And a decade after System C’s debut, the idea of using high level programming language to do hardware design revived. And this time, Scala has replaced C++ to do the job, and Chisel and SpinalHDL are the two offspring of such idea. To distinguish them from VHDL/Verilog/SystemVerilog, people have coined a tech term for them: HCL (Hardware Construction Language). As mentioned in previous episode, for HCL, our bet is on the SpinalHDL side. And here is why:
1. The design done in HDL (VHDL/Verilog/SystemVerilog) is still too wordy. Practically, for the same design, the number of lines in SpinalHDL is only half of that for SystemVerilog.
2.The HDL (VHDL/Verilog/SystemVerilog) lacks high level data structure for design. Although SystemVerilog has introduced some high-level features like OO, they are mainly used for verification. The design in HDL is still done with very low-level data structure (like always for Verilog or process for VHDL). Again, to use programming language as analogy, HDL is more like Assembly while the HCL is more like modern high level programming language.
3. To choose SpinalHDL over Chisel, the SpinalHDL holds certain advantages like those shown here.
As for the synthesis flow, the SpinalHDL relies on SBT as the make for build. And it will produce VHDL, Verilog or SystemVerilog as the result.
Simulation Flow for SpinalHDL
And for simulation, behind the scene, the SpinalHDL will be compiled into Verilog, and simulated by Verilator. The verilator will actually turn the Verilog into C++, and running the simulation under GCC and JDK.
And please don’t worry about those details at this point, as we will elaborate on SpinalHDL in later episodes.
For the next episode, we will get hands-on for SpinalHDL, starting by setting up the development environment and a hello-world example.
Hello, everyone. Welcome to FPGA limerick. This channel will bring in a series of talks on FPGA design, including both RTL and software, as well as some domain specific knowledges.
The purpose of those talks is to lay the foundation for PulseRain Technology’s open-source IP portfolio along with the whole design methodology and design flow.
And of course, it is also for our own edification.
The main topics to be covered are the following:
First of all, we will discuss the Hardware Design Language for RTL. As for PulseRain Technology, the main HDL that we use is SpinalHDL, plus some Systemverilog / Verilog. As you might know, SpinalHDL can produce Verilog or VHDL as its output. In this regard, we will give an in-depth talk on SpinalHDL, as it is becoming our “official language” for RTL design and verification. We will take a close look at the evolution of hardware design language to demonstrate the highlights of SpinalHDL. In addition to that, we will also show the nitty-gritty of SpinalHDL through hands-on knowledges.
Secondly, we will talk about the simulation / verification for various IPs. The main simulation tools we are gonna use are verilator and cocotb. The verilator will be seamlessly integrated into SpinalHDL environment. And it will also be used on cocotb. Cocotb is a good complement to SpinalHDL by providing a Python testbench and an abundance of library such as AXI bus.
Thirdly, we will usher in PulseRain Technology’s open-source IP portfolio, which also covers various domain knowledges for things like SPI, I2C, UART, Micro-SD card, RISC-V processor etc.
And in addition, if you, the audience, have other interesting topics that you would like us to cover, you are welcome to post your suggestions as the YouTube comments.