The main topics to be covered are the following:
First of all, we will discuss the Hardware Design Language for RTL. As for PulseRain Technology, the main HDL that we use is SpinalHDL, plus some Systemverilog / Verilog. As you might know, SpinalHDL can produce Verilog or VHDL as its output. In this regard, we will give an in-depth talk on SpinalHDL, as it is becoming our “official language” for RTL design and verification. We will take a close look at the evolution of hardware design language to demonstrate the highlights of SpinalHDL. In addition to that, we will also show the nitty-gritty of SpinalHDL through hands-on knowledges.
Secondly, we will talk about the simulation / verification for various IPs. The main simulation tools we are gonna use are verilator and cocotb. The verilator will be seamlessly integrated into SpinalHDL environment. And it will also be used on cocotb. Cocotb is a good complement to SpinalHDL by providing a Python testbench and an abundance of library such as AXI bus.
Thirdly, we will usher in PulseRain Technology’s open-source IP portfolio, which also covers various domain knowledges for things like SPI, I2C, UART, Micro-SD card, RISC-V processor etc.
And in addition, if you, the audience, have other interesting topics that you would like us to cover, you are welcome to post your suggestions as the YouTube comments.
Ok, now let’s talk about a few logistics issues:
*) YouTube Playlist
To keep each talk short and sweet, we plan to make each episode less than 15 minutes.
*) Github repo, all the code and documents can be found in this repo:
BTW, the license term for this repo is Apache 2.0
*) Companion Blog
And also, we have a companion blog as a supplement to the videos. You can find the blog at https://fpga.pulserain.com. It is pretty much the text version of the same talk.