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Limerick(9) - Cocotb Tutorial: Test Bench Structure

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Hello, everyone. Welcome to the nineth episode of FPGA limerick. In this episode, we will take a deep look into the test bench structure of cocotb. As we know, cocotb stands for Coroutine Cosimulation Testbench. So before we start, we might ask ourselves: What is coroutine? In multi-task scenario, coroutine can be viewed as a collaborative non-preemptive thread. The following shows two coroutines calling each other, with yield at every step. And the execution order will always be 1, 2, 3, 4, 5 In cocotb, the coroutine is marked by putting “async” in front of the function name. And the yield is done with “await” command. We will soon see the details when it comes to the test bench next. The Classic Way If you read the official document of cocotb, it uses Makefile to organize the test bench. And for each coroutine, it will be decorated @cocotb.test(), like the following example: @cocotb.test() async def test_xxx(dut):    … However, what we will recommend is something differe...
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Limerick(8) - Cocotb Tutorial: Introduction

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Hello everyone, welcome to the eighth episode of FPGA Limerick. In this episode, we will talk about the cocotb to make Python based test bench. And to show why we choose cocotb for verification, let’s visit other possible options: Overview 1. Verification, the old-fashioned way: Use Verilog/VHDL to make both testbench and DUT: As of today, a lot of companies still do things this way. However, because the Verilog/VHDL lacks the features offered by high level programming language, this method becomes very inflexible, verbose and unproductive. 2. Verification: HVL + HDL 3. Verification / Design with System Verilog Although System Verilog did a good job introducing high level programming language features, such as Object Oriented syntax, it is still considered too verbose and low level comparing to newer programming languages like Python. And thus comes the cocotb. Cocotb stands for Coroutine Cosimulation Testbench. It is a Python based verification framework. And practically it can be a g...
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Limerick(7) - Build/Run Hello World for FPGA Board

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  Hello, everyone. Welcome to the seventh episode of FPGA limerick. In this episode, we will get our hands dirty, to build the Hello Word example in the previous episodes, and to load it onto a FPGA board for Blinking LED. First of all, as we mentioned in the first episode, we will use the Arty A7-100T board from Digilent as our main FPGA development board. The board can be found in this link: https://digilent.com/shop/arty-a7-100t-artix-7-fpga-development-board/   Tool Installation And to build the Hello Word example, we need to do the following: 1. Install the Vivado The Vivado can be downloaded from https://www.xilinx.com/support/download.html We will use Vivado 2022.2 as our Vivado version. Please download and install it from Xilinx website. If you want to save disk space, you can only install 7 Series for devices.    And Digilent also has some detailed instructions for installing the tools: https://digilent.com/reference/programmable-logic/guides/installing-viva...
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Limerick(6) - SpinalHDL Tutorial: the Simulation Flow of Hello World

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Hello, everyone. Welcome to the sixth episode of FPGA limerick. In this episode, we will take a close look at the simulation flow of SpinalHDL. And we will use the Hello World as an example for demonstration purpose. Verification Methodology Generally speaking, when it comes to digital circuits, there are two approaches for verification.  1. Formal Verification The formal verification is more like a math approach, because basically every digital circuit is nothing but a mapping from input to output, which mathematically fits the definition of Function.  In that sense, the DUT is treated as a math function, whose property is described by SVA (System Verilog Assertion), as illustrated below: As it is like a math approach, there is no need to prepare test vectors for input and output. And the formal verification tool will use analytic method to check the DUT against those SVAs, and to make sure those properties are satisfied in all conditions. SpinalHDL also supports Formal Verif...
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Limerick(5) - SpinalHDL Tutorial: the Design Flow of Hello World

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Hello, everyone! Welcome to the fifth episode of FPGA limerick. In this episode, we will take a close look at the “Hello World” example for SpinalHDL. And based on that, we will also demonstrate the basic design flow for SpinalHDL. As mentioned in previous episodes, the Hello World can be checked out like git clone --depth 1 --branch v1.1.4 https://github.com/PulseRain/FpgaLimerick.git   The folder structure of Hello World And for a fresh checkout, it has the following files: *) Files at the top level                 build.sbt : configuration file for SBG                 .scalafix.conf : configuration file for scalafix (linter)                 scalastyle-config.xml : configuration file for scalastyle (linter)      ...
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