FPGA Limerick

Hello, everyone. Welcome to the fourth episode of FPGA limerick. In this episode, we will talk about the linter, formatter, logging and editor for SpinalHDL. However, as we all know, the concepts like linter, formatter etc. are universal. They are not only confined to SpinalHDL. So we will expand the scope to other languages when it is necessary. Linter for C/C++ Maybe we can start with a more popular language like C/C++. An often-used linter for C/C++ is clang-tidy . On Ubuntu, (which is the Linux distro we choose for WSL), it can be installed like sudo apt install clang-tidy And you can use the following to check a C/C++ source file: clang-tidy -checks=* file_name.cpp And you can use the following inline comment to ignore a certain warning, like // NOLINT(cppcoreguidelines-avoid-magic-numbers, readability-magic-numbers) Or simply just // NOLINT   Formatter for C/C++ An often-used formatter for C/C++ is clang-formatter, which can be installed on Ubuntu like ...

Hello, everyone. Welcome to the third episode of FPGA limerick. In this episode, we will get hands-on for SpinalHDL, starting by setting up the Development Environment. Setup for Windows/MSYS2 As mentioned in the first episode, we will use Windows 11 + MSYS2 + WSL2 as our host platform. And we will start by MSYS2 first. To install MSYS2, please open your browser and go to https://www.msys2.org/ And at this point, we will install the following version for MSYS2: https://github.com/msys2/msys2-installer/releases/download/2023-01-27/msys2-x86_64-20230127.exe After the MSYS2 is installed, it needs to be setup for additional packages. Please open the MSYS2 MINGW64 from Windows Start Menu, and type in the following: pacman -Syuu After this command, the MSYS2 window will be closed automatically. Please reopen it through Windows Start Menu (Please choose MSYS2 MINGW64 again), and type in pacman -Syuu again. Then please type in the following: pacman -S --needed base-devel min...

Hello, everyone. Welcome to the second episode of FPGA limerick. In this episode, we will talk about the benefit of SpinalHDL. And we will start by visiting the evolution history of HDL (Hardware Description Language). History 101 for HDL/HVL In the beginning of time when digital circuits started to emerge, everything was handcrafted. A typical example of such design practice is the ubiquitous presence of Texas Instruments’ 74-Series IC back then. At that time, a large digital circuit was usually composed of multiple discrete ICs (AND gate, OR gate, FlipFlop etc.). And the whole system was often bulky and slow. But as Moore’s law settles in, the scale of digital circuit grew exponentially over the years. It calls for a better methodology and automation in design. And thus comes in the hardware description language. The first hardware description language is VHDL. It was developed in 1983 under the funding of the Department of Defense. It was such a big deal at that time, and the VHDL w...

Hello, everyone. Welcome to FPGA limerick. This channel will bring in a series of talks on FPGA design, including both RTL and software, as well as some domain specific knowledges.  The purpose of those talks is to lay the foundation for PulseRain Technology’s open-source IP portfolio along with the whole design methodology and design flow. And of course, it is also for our own edification.  The main topics to be covered are the following: First of all, we will discuss the Hardware Design Language for RTL. As for PulseRain Technology, the main HDL that we use is SpinalHDL, plus some Systemverilog / Verilog. As you might know, SpinalHDL can produce Verilog or VHDL as its output. In this regard, we will give an in-depth talk on SpinalHDL, as it is becoming our “official language” for RTL design and verification. We will take a close look at the evolution of hardware design language to demonstrate the highlights of SpinalHDL. In addition to that, we will also show the nitty-gritt...

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